Modern electronic design processes often generate a schematic design and then proceeds through various phases from the schematic design to create a physical layout. For example, electronic design processes may start with design planning or floorplanning to generate a floorplan and proceed through at least the placement and routing process to generate a fully routed physical layout. The goals of design planning or floorplanning may include, for example, silicon utilization, increase of design performance, etc.
Furthermore, a physical layout may be constructed as a flat layout where every circuit component design in placed in a single hierarchy despite the fact that certain circuit component designs may functionally belong to a sub-module which may in turn belongs to a module that further reports to a cell in an IC (integrated circuit) design. Such a flat layout has its own advantages. For example, a flat layout may be easier for placement and routing although dealing with millions or billions of design components during the design planning or floorplanning stage is impractical at best, if not entire impossible. Flat layouts have their own disadvantages. For example, connectivity search processes are slow for flat layouts, especially when the design size or complexity increases.
Rather than a flat layout, some approaches generate a hierarchical layout with either a bottom-up or a top-down approach. A top-down approach begins the implementation process at the top or highest hierarchy and proceeds to lower hierarchies until it reaches the lowest hierarchy to complete an IC design. With the top-down approach, the functional cells at a higher hierarchy may be brought into the layout canvas while each cell include its own pins, ports, or terminals (collectively pin for singular or pins for plural hereinafter). The details of these functional cells at lower hierarchies are not yet exposed and will be designed at respective lower hierarchies as the top-down approach migrates to lower hierarchies. As a result of the non-exposure or unavailability of lower hierarchies (e.g., the lower hierarchies have not yet been implemented), a circuit designer working on the higher hierarchy may need to estimate the size of each cell and guess or guesstimate the locations of pins or terminals for the cell. The estimated cell may be too big to waste invaluable space on silicon or may be too small to accommodate all the devices therein.
In addition to the manual efforts to create the location, identification, etc. for a pin of a cell, these guesstimated pin or terminal locations unlikely to be optimal for connecting with the pins or ports of the devices within the cell. Either way, multiple iterations may be required for even a single cell. In addition, even if the circuit designer knows how these pins are connected to each other, the circuit designer may only align or offset these pins by manipulating the cell. In the event that a designer groups a set of components or cells and intends to create a logical cell for the set, the pins of the logical cell or their identifications thereof (e.g., names of the pins) have to be manually created. The designer will then have to find the corresponding pin identifications in the schematic design and associated these manually created identifications with the corresponding pin identifications.
Bottom-up approaches begin with the design of discrete circuit components and proceed to higher hierarchies as the designs of lower hierarchies are complete until the design for the top or highest hierarchy is complete. In these bottom-up approaches, pins and their identifications as well as locations are determined at lower hierarchies in their respective cells. At the higher hierarchies, these pins often present a challenge to routing these pins of an actual or virtual cell because these pins are determined individually for each cell and independent of each other and may thus cause misalignment of pins or terminals at higher hierarchies where these cells are assembled and supposed to be interconnected. To rectify these problems such as pin or terminal misalignment at higher hierarchies, the design process must return to the lower hierarchies where the devices with the misaligned pins are placed, adjust the placement of the devices, and determine whether the pins or terminals are aligned at the next higher hierarchy. These conventional approaches must then proceed to the next higher hierarchy to determine whether there exist other misalignment problems. These conventional approaches may thus iterate multiple times until an acceptable or desirable solution is found. Therefore, there is a need for a better approach to manipulate the hierarchies of an electronic design to effectively and efficiently create a cell for a group of devices.
Despite these shortfalls, hierarchical layout generation may be more beneficial for design planning or floorplanning because circuit component designs may be encapsulated in different hierarchies and may thus be manipulated with ease by manipulating higher hierarchy cells or blocks. Hierarchical layouts nevertheless present their own shortcomings. For example, hierarchical layouts are difficult for placement or routing of the design. Hierarchical layouts also consume much more computational resources at least during the design planning or floorplanning stage. For example, every hierarchy in the layout needs to be saved at least in a persistent or non-persistent form and thus consumes much more disk I/O (input/output) or network I/O, especially when the layout is still at the early planning stage where circuit component designs or blocks are often moved around or modified.
Conventional design planning tools or floorplanners often operate on individual component basis and use various techniques (e.g., force-based techniques) to pull or push components on individual basis until certain criteria are met. A designer or an EDA (electronic design automation) tool has to literally select individual circuit component designs and move the individually selected circuit component designs in a layout canvas until certain criteria are met. Although some EDA tools have attempted to improve this shortcoming by allowing designers to generate a module so that the generated module may be manipulated as a block, such attempts nevertheless fall short for the same reasons—individual identification and selection of circuit component designs during at least the module generation process. In addition, such module generation processes disturb the physical hierarchy that corresponds to the schematic hierarchy when a module is generated for a group of circuit component designs. Therefore, there is a need for implementing design planning for an integrated circuit design with virtual hierarchies to address at least the aforementioned problems and to provide a more computational resource-efficient and effective approach for early physical design stages such as floorplanning, placement, etc.
With the advent of virtual hierarchies for electronic designs as listed in the U.S. patent applications listed in the Section entitled Cross Reference to Related U.S. Patent Applications, there have been no effective techniques to abstract virtual hierarchies, especially in a flat portion of a layout or a flat layout. The users are thus presented with all the layout circuit component designs although encompassed in one or more virtual hierarchies.
Therefore, there exists a need for methods, systems, and computer program products for dynamically abstracting virtual hierarchies for an electronic design.